1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to suppression of data destruction in a semiconductor integrated circuit device having a ferroelectric memory.
2. Description of the Related Art
A ferroelectric capacitor changes in polarization state by applying a voltage across the capacitor. A ferroelectric memory is a memory which reads out, as a signal, charges emitted from a ferroelectric capacitor when a predetermined voltage is applied to the capacitor to change its polarization state. For example, when a positive voltage is applied to a ferroelectric which stores a negative signal, the polarization is inverted to read out many charges from the capacitor. The polarization state does not change unless a voltage is applied to the capacitor. If an unexpected voltage is applied to the ferroelectric capacitor due to noise or the like, data is destroyed. In the ferroelectric memory, application of voltage noise to a memory cell capacitor which is not accessed must be prevented as much as possible.
FIG. 19 shows an example of a ferroelectric memory.
This ferroelectric memory is a memory which includes series connected memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor inbetween the two terminals, hereafter named “Series connected TC unit type ferroelectric RAM”.
In the series connected TC unit type ferroelectric RAM, all word lines WL0 to WL3 are fixed to a “HIGH” potential in the standby state, and the two terminals of the ferroelectric capacitor are short-circuited. This completely suppresses application of a voltage to the memory cell capacitor in the standby state.
FIG. 20 shows an active state in which one of series-connected memory cells is accessed. In FIG. 20, the word line WL0 is selected to hold WL0=“LOW” level. Further, a block selection line BS1 is activated to BS1=“HIGH” level. The potential of a plate line PL is fixed to PL=VPLL in the standby state. When a memory cell is accessed, the plate line PL changes to PL=VINT and is activated. In this case, VPLL is typically 0V, and VINT is 2.5V. Since the word line WL0=“LOW” level, a transistor T00 is turned off, a voltage is applied across a memory cell capacitor C00, and charges corresponding to the held data are transferred to a bit line BL. Another plate line /PL is not activated and maintains /PL=VPLL. A block selection line BS2 also maintains BS2=“LOW” level. No data is transferred to a bit line /BL adjacent to the bit line BL, and the bit line /BL is used as a complementary bit line.
Attention is given to an unselected memory cell C10. The unselected plate line /PL is inactive and thus fixed to the potential VPLL. The block selection line BS2 is also inactive, and C10 has a node connection relationship shown in FIG. 21. More specifically, one terminal of the capacitor C10 is connected to the inactive plate line /PL=VPLL, and the other terminal of the capacitor C10 is connected to a floating node N2 between two “OFF” transistors T10 and TB2 having a “LOW”-level gate potential. The potential of the bit line /BL is amplified to VSS (=0V) or VINT in accordance with data of a memory cell selected by a sense amplifier. Assume that /BL=VINT. The “OFF” transistor TB2 has a potential difference between its source and drain. Even if the gate potential of the transistor TB2 is set at “LOW” level and it is OFF, a current is not cut off by an infinite resistance value, and a finite subthreshold current flows through its source-drain path. Since the node N2 is floating, the subthreshold current changes the potential of the node N2. If the chip activation time is prolonged, the potential of the node N2 may change by, e.g., 100 mV or more. When this happens, a voltage is applied to the capacitor C10, destroying data.
To prevent this, a method of discharging the potential of a bit line to 0V at once regardless of data in a memory cell has been proposed (see, e.g., reference 1). According to this method, in FIG. 21, potentials on the other-terminal sides of the source-drain paths of the two transistors which sandwich the floating node N2 are the potential VPLL and a discharge bit line potential of 0V. The above problem does not occur at VPLL=0V.
Further, a method of setting the standby voltage VPLL of a plate line to a value other than 0V has also been proposed (see, e.g., reference 2). It is difficult to activate the chip for a long time for such ferroelectric memory.
reference 1: Jpn. Pat. Appln. KOKAI Publication No. 2000-339973
reference 2: U.S. Pat. No. 6,493,251